Real Intent Attends 9th Annual International MAPLD Conference, Showcases Automatic Formal, Clock and Timing Verification Software for Electronic Desig17 September 2006
Who
Real Intent, the leader in formal electronic design verification from spec to sign-off
What:
Real Intent's exhibit at the 9th Annual International Military and Aerospace Applications of Programmable Devices and Technologies (MAPLD) conference with demonstrations showing how formal verification technology improves electronic design timing, verification, productivity and quality.
When/Where
September 26-28, 2006 Booth #39 Ronald Reagan Building and International Trade Center Washington, D.C.
Information and Registration:
To set an appointment with Real Intent, please contact Rich Faris 408-839- 6510. For more information about Real Intent, please visit www.realintent.com. Please visit http://www.klabs.org/mapld06/ for more information about MAPLD. The conference is open to US and foreign participation and is unclassified. For related information, please see the NASA Office of Logic Design Web Site (http://klabs.org).
About Real Intent's EnVision Family
Highlighted Links Real Intent
MAPLD Conference
With Conquest, users can verify their design using Property Specification Language (PSL) assertions, SystemVerilog Assertions (SVA), or Open Verification Library (OVL) checkers. Conquest uses advanced static formal verification technology to verify correctness of electronic designs.
Ascent offers automatic checks derived from the Register Transfer Level (RTL) design to verify logic and find bugs even before simulation. It finds sequential design errors, including array bounds violations, full and parallel case pragma violations, Finite State Machine (FSM) deadlocks and dead code, without testbenches or vectors. It supports PSL and SVA constraints and includes the Ascent SimPortal, which links to dynamic simulation.
Clock Intent Verification verifies the functionality of the user's cross domain clocking scheme and quickly identifies errors with its new debugging features.
PureTime, a timing-exception verifier, detects timing exception errors that create schedule delays, chip respins or failing hardware. It proves the correctness of timing exceptions created by designers, or those delivered with Intellectual Property (IP), using exhaustive formal analysis. PureTime works throughout the entire design flow, with RTL or design netlists.
About Real Intent
Real Intent is extending breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent's products dramatically improve the functional verification efficiency of leading edge application-specific integrated circuit (ASIC), system-on-chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 40 major electronics design houses, including Sun Microsystems, ATI, Marvell Technology Group, nVidia, and NEC Electronics, use Real Intent software.
Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700, fax: (408) 737-1962, web: www.realintent.com, e-mail: info@realintent.com.
EnVision, Conquest, Ascent, Convergence Engine, SimPortal, PureTime, Clock Intent Verification are trademarks of Real Intent, Inc. All other trademarks or registered trademarks are property of their respective owners.
Press contacts: Rich Faris Real Intent Vice President Marketing and Business Development (408) 830-0700 x212 Email Contact
Georgia Marszalek Valley PR for Real Intent (650) 345-7477 Email Contact
SOURCE: Real Intent
Source: marketwire
All trademarks and copyrighted information contained herein are the property of their respective owners.
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